Generally, the choice of the metallic material is linked to the resistivity of the metal which is one of the key characteristics in the choice of electrical interconnects. In practice, the resistivity acts on at least three parameters which are the signal propagation time, voltage drop and heating by Joule effect. A low resistivity of the conductors is therefore an essential parameter in choosing the materials used.
Copper is one of the solid metals, with silver, that exhibits the lowest electrical resistivity. This is one of the reasons, with the resistance to the electromigration phenomenon, for which it is currently used in very high density integration.
Nevertheless, the copper interconnects come up against two kinds of problems which are that copper is difficult to etch and that it exhibits a high capability for diffusion into numerous materials. This diffusion can lead to the short-circuiting of adjacent tracks, and therefore to an overall circuit malfunction.
The Damascene method described hereinbelow and illustrated in FIG. 1 was developed to overcome these two drawbacks.
It relies notably on a succession of steps which are the following: deposition of a layer of inter-level insulating dielectric, etching of the interconnect patterns, consisting of the lines and vias in the dielectric layer, notably by reactive ion etching (commonly abbreviated RIE), deposition of a barrier layer in the dielectric, used to prevent the migration of the copper, filling of the lines and vias with the copper, elimination of the excess copper by mechanical/chemical polishing.
The copper deposit is produced by electrodeposition, a method that offers good performance in terms of deposit quality, by allowing an effective filling of the trenches. This method can, for example, be based on galvanic copper deposition from a bath containing notably copper sulphate (CuSO4) and additives.
The various steps of this method are illustrated in FIG. 1.
More specifically, after the deposition of an encapsulation dielectric 10, on a first level of interconnects N1, corresponding to the step 1a, trenches Ti are produced by etching in places intended for the production of the interconnects (step 1b) within a substrate S made of dielectrics; a diffusion barrier 11 then a conductive layer 12 are deposited on the surface of the trenches (step 1c) in order to allow the filling of the trenches with the copper Cu by electrochemistry (step 1d). After a bake step, the excess copper on the surface is removed in a mechanical-chemical polishing operation (step 1e), this latter operation commonly being called CMP.
The CMP method is a method of smoothing and planarizing surfaces which combines chemical and mechanical actions, using a chemical etching and mechanical polishing with free abrasive mixture. Mechanical lapping alone causes too much damage on the surfaces and wet etching alone does not yield good planarization. Since the chemical reactions are isotropic, they attack the materials without distinction in all directions. The CMP method combines the two effects at the same time.
However, in environments of small dimensions, typically less than a few hundreds of nanometers (approximately 200 nm), the properties of the copper change. Thus, the resistivity of the copper increases when the line width decreases as described in the article by W. Steinhoegl, G. Schindler and M. Engelhardt, entitled “Unraveling the mysteries behind size effects in metallization systems”, Semiconductor International, January 2005.
In this respect, FIG. 2 illustrates the trend of the resistivity of copper lines according to the line width corresponding to the width of the trenches, obtained using the Damascene method.
A number of factors must be taken into account. First of all, to avoid the formation of cavities in the lines, the use of additives during the electrochemical growth of the copper is necessary. These additives can be incorporated in the copper in the form of impurities on deposition and thus modify its properties. However, the main factors behind this trend in resistivity are linked to the geometry of the lines, notably their dimensions. It appears that the grain size of a material is limited by the confinement, the smallest dimension of the medium. This phenomenon is notably described in the article by Q-T. Jiang, M. Nowell; B. Foran, A. Frank, R. H. Haveman, V. Parihan, R. A. Augur and J. D. Luttmer, entitled “Analysis of copper grains in damascene trenches after rapid thermal processing or furnace anneals”, Journal of Electronic Materials 31(1): 10-15, January 2002.
Thus, in narrow lines, the grain size becomes of the order of magnitude of the average free path of the electrons in the solid copper (i.e. 38 nm at 300 K). The electrons then have a tendency to diffuse over the grain joints, through the passage of current.
Furthermore, for small line sizes (typically less than 100 nm wide), a small grain size is a cause that aggravates the phenomena associated with electromigration that reduce the life of the interconnects, the grain joints being possible atom diffusion paths, as described in the article by Changsunp Ryu, Kee-Won Kwon, Alvib L. S. Loke, Haebum Lee, Takeshi Nogami, Valery M. Dubin, Rahim A. Kavari, Gary W. Ray, and S. Simon Wong, IEEE TRANSACTIONS ON ELECTRON DEVICES, 46 (6) (1999), 1113-1120.
The microstructure of the copper is linked to the technological method used for its integration, and typically according to the Damascene method, the grain size after the electrochemical deposition is small. A grain growth bake is applied and during this bake, the surplus copper is still present.
The grain growth mechanism is carried out according to the scheme illustrated in FIG. 3. The step 3a relates to the phase just after the electrochemical deposition in which the grains are small.
In addition to growth of the grains in the line, an invasion of the grains from the excess thickness into the trench is observed, as illustrated in step 3b, and this mechanism can be extended to a total invasion of the trench as illustrated in step 3c. 
It has been shown that the extent of this mechanism depends on the bake temperature and on the dimensions: “Cu grain growth in interconnects trenches—Experimental characterization of the overburden effect” Carreau V., Maitrejean S., Brechet Y., Verdier M., Boucu D., Passemard G., Microelectronic Engineering, Volume 85, Issue 10, October 2008, pages 2133-2136.
Thus, for bakes at 150 degrees, a limit invasion depth has been determined according to the width of the line as shown by the curve in FIG. 4 which illustrates the invasion depth as a function of the trench width for copper lines baked at 150° C., for 6 hours. This limit depth decreases when the line width decreases.
However, it has also been shown that this growth mechanism makes it possible to obtain a larger grain size in the lines.
An alternative solution to the thermal bake for obtaining large grains is ion implantation. This method uses the density of crystalline defects as the driving force in the movement of grain joints.
The copper grains which have a greater density of defects are consumed to the detriment of the grains that have fewer defects. Given a constant volume, the number of grains decreases so that their average size increases.
Under the impact of an ion beam, crystalline defects appear in a material according to the crystalline orientation of the latter. Two grain populations must then be distinguished: the grains that are oriented so as to channel the incident ions and the others as described in the article by R. Spolenak, L. Sauter, C. Eberl, entitled “Reversible orientation-biased grain growth in thin metal films induced by a focused ion beam”, Scripta Materiala, 53, 1291-1296, 2005.
The grains that channel the ions grow at the expense of the grains that do not channel the incident ions as illustrated in FIG. 5. Under the action of an ion implantation flux Fi, the grains that channel the ions referenced Gci can grow at the expense of the grains that do not channel the ions, situated at the periphery of the grain Gci.
The feasibility of this technique has been demonstrated by the ion implantation of Ga+ ions (R. Spolenak, L. Sauter, C. Eberl, Reversible orientation-biased grain growth in thin metal films induced by a focused ion beam, Scripta Materiala, 53, 1291-1296, 2005) and Ar+ ions (S. Olliges, P. Gruber, A. Bardill, D. Ehrler, H. D. Cartanjen, R. Spolenak, Converting polycrystals into single crystal-selective grain growth by high-energy ion bombardment, Acta Materiala, 54, 5393-5300, 2006) in thin films. The effects of the ion implantation on the grain size can be detected up to depths of approximately 500 nm.
Generally, the growth of the copper layer is polycrystalline. The concept of grain joints is defined by the interface between two crystalline domains in a polycrystalline structure.
The size of the grains depends on the surface of the substrate, the growth conditions and the dimensions of the trenches.
Results of crystalline orientation measurements in structures of Damascene type show that the grains deriving from the invasion of the excess thickness have an orientation that is different from those deriving from the growth in the connect line, as is described in the article by B. Kaouache, S. Labat, O. Thomas, S. Maitrejean, V. Carreau: “Texture and strain in narrow copper damascene interconnect lines: An X-ray diffraction analysis” Microelectronic Engineering, Volume 85, Issue 10, October 2008, pages 2175-2178.
The grains deriving from the growth in the line are oriented with a direction <111> perpendicular to the substrate and a direction <110> in the direction of the line.
The grains deriving from the invasion show a direction <001> perpendicular to the substrate.